1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of Related Art
Japanese Patent Application Publication No. 2008-135522 (JP 2008-135522 A) describes a semiconductor device in which an element region and a termination region are formed in a semiconductor substrate. In the element region, a plurality of linear trench gate electrodes is formed, and in the termination region, a plurality of termination trenches provided around the plurality of trench gate electrodes is formed. P-type floating regions are formed on bottom faces of the termination trenches. The floating regions are surrounded by an n-type drift region. The semiconductor device is configured such that an interval between floating regions adjacent to each other is optimized so as to improve uniformity of breakdown voltage in the termination region.
In recent years, development of a semiconductor device with low loss has been desired. As one approach to attain low loss of a semiconductor device, an on-resistance may be reduced. In order to reduce the on-resistance, it is conceivable that an impurity concentration in a drift region is increased. However, if the impurity concentration of the drift region is increased, respective breakdown voltages in an element region and in a termination region might be decreased. When the breakdown voltage of the termination region becomes the breakdown voltage of the element region or less, avalanche breakdown occurs in the termination region. Generally, the termination region has a smaller area than the element region. Therefore, if a breakdown current flows through the termination region, a temperature of the termination region easily becomes high, which is unfavorable. Accordingly, there is such a demand that the breakdown voltage of the termination region is set higher than the breakdown voltage of the element region so that avalanche breakdown occurs in the element region.